With a convergence of information technology (IT) devices and the trend of light, thin, short, and small devices, a system-on-chip (SoC) in which several high-quality IT devices are integrated on one chip is under development. In particular, among the techniques of implementing the SOC, an importance of a bus system for connecting several processing devices and for enabling mutual communication is gradually emerged. However, since a system integration level is increased and an information exchange amount between the processing devices is rapidly increased, a conventional shared bus structure is less frequently utilized than before in a high-quality SoC due to a bandwidth limit. In order to overcome the bandwidth limit and to facilitate a design of the high-quality SOC, a network-on-chip (NoC) technique is proposed.
Meanwhile, for a precise system-level power management, the NoC technique uses a voltage-frequency-island (VFI) scheme proposed to cluster cores using the same voltage-frequency into the same island among a plurality of cores.
However, when the NoC is constructed of heterogeneous cores having not only different voltages and frequencies but also different communication features, this scheme cannot construct the cores in a topological manner with a structure required for a power management.
In addition, when the heterogeneous cores are clustered in this manner, there is a problem in that it is difficult for the electronic device to provide an NoC with a desired size since the NoC is increased in size greater than a case of clustering homogenous cores.